Recent years have seen an increased interest in field emitter displays. This is attributable to the fact that such displays can fulfill the goal of hang-on-the-wall flat panel television displays with diagonals in the range of 20 to 60 inches, among other uses. Such other uses include lap top computer display screens and instrument panel displays to mention a few applications. Some field emitter displays, or flat panel displays, operate on the same physical principle as fluorescent lamps. An emitted electron excites a gas discharge generates ultraviolet light (photons). The ultraviolet light then imparts energy to a phosphor which re-emits visible light.
Other field emitter displays operate on the same physical principals as cathode ray tube (CRT) based displays. Excited electrons are guided to a phosphor target which excite the phosphor directly. The phosphor then emits photons in the visible spectrum. Silicon substrate field emitter arrays are one source for creating similar displays. Both type methods of operation for field emitter displays rely on an array of field emitter tips.
Silicon substrate field emitter arrays have been previously described for flat panel field emission displays. Application of silicon substrate field emitter arrays into large area manufacture for use in large size displays presents costly and lengthy processing requirements. Typical silicon field emitter arrays have only been produced according to lengthy, conventional, integrated circuit technology, e.g., by masking silicon substrates and then either etching or oxidizing to produce cones of silicon with points for field emitters. The cones of silicon can then be utilized directly or undergo further processing to cover the points with some inert metal or low work function material.
Another problem with silicon based field emitter processing involves emitter tip to gate distance. The resolution of a field emission display is a function of a number of factors, including emitter tip sharpness, alignment and spacing of the gates, or grid openings, which surround the tips. This distance partly determines the turn-on voltage, the voltage difference required between the tip and the grid to start emitting electrons. Typically, the smaller the distance, the lower the turn-on voltage for a given field emitter, and hence lower power dissipation. A low turn-on voltage also improves the beam optics and the speed at which the display can change. Thus it is desirable to minimize the emitter tip to gate distance in the development of field emission devices (FED).
There are numerous methods to fabricate FEDs. One such popular technique in the industry includes the “Spindt” method, named after an early patented process. Spindt, et. al. discuss field emission cathode structures in U.S. Pat. Nos. 3,665,241, 3,755,704, and 3,812,559. Generally, the Spindt technique entails the conventional steps of masking insulator layers and then includes lengthy etching, oxidation, and deposition steps. In the push for more streamlined fabrication processes, the Spindt method is no longer the most efficient approach. Moreover, the Spindt process does not resolve or necessarily address the problem of gate to emitter tip distance.
The emitter tip to gate spacing is generally determined by the thickness of the dielectric layer in place between the two. One method of achieving a smaller emitter tip to gate distance is to deposit a thinner dielectric, or insulator layer. However, this approach has the negative consequence of increasing the capacitance between the gate and substrate regions. In turn, the increased capacitance increases the response time of the field emission device.
A more recent technique includes the use of chemical mechanical planarization (CMP) and an insulator reflow step. One such method is presented in U.S. Pat. No. 5,229,331, entitled “Method to Form Self-Aligned Gate Structures Around Cold Cathode Emitter Tips Using Chemical Mechanical Polishing Technology,” which is assigned to the same assignee as the present invention. Unfortunately, an insulator reflow process generally involves the use of an extra processing step to lay down an extra insulator layer. Also, the typical reflow dielectric materials employed, e.g., borophosphorus silicate glass (BPSG), require high processing temperatures to generate the reflow. This fact negatively impacts the thermal budget available in the fabrication sequence.
Thus, it is desirable to develop a controlled size in emitter tip formation in a more streamlined process. Further, what is needed is a more efficient method to control the gate to emitter tip proximity in self aligned structures.